A network processor generally controls the flow of packets between a physical transmission medium, such as a physical layer portion of, e.g., an asynchronous transfer mode (ATM) network or synchronous optical network (SONET), and a switch fabric in a router or other type of packet switch. Dynamic random access memories (DRAMs) are a preferred storage technology for use in conjunction with such network processors, in that DRAMs can provide a large storage capacity at a limited power consumption.
DRAMs within or otherwise associated with a network processor are typically arranged in the form of multiple memory banks. Consecutive read or write accesses to an address or addresses within a given one of the banks will require waiting a random cycle time Trc for completion of a required access pre-charge process. However, consecutive accesses to even the same address within different banks do not experience this Trc wait time, which is also referred to herein as the bank conflict penalty.
Static random access memories (SRAMs) avoid the bank conflict penalty altogether. That is, any address in the memory can be accessed in a fixed time without incurring the Trc wait time associated with DRAMs. The drawback of SRAMS, however, is that their storage capacity is typically an order of magnitude lower, and their power consumption is typically two orders of magnitude higher, relative to comparably-sized DRAMs.
A number of DRAMs known in the art are specifically configured to reduce the Trc wait time described above. For example, a so-called fast cycle DRAM (FCDRAM) is particularly designed to exhibit a minimal Trc. A more particular example of an FCDRAM, commercially available from Toshiba, is identified by part number TC59LM814CFT-50. In this particular type of FCDRAM, the random cycle time Trc is limited to 5T, where T denotes the memory clock period. A memory access, either read or write, requires two clock periods, and maximum data throughput is achieved by using a so-called “four-burst” mode. For example, using a 200 MHz memory clock and an FCDRAM configured in four banks, with each of the banks including 4M memory words of 16 bits each, the memory clock period T is 5 nanoseconds and Trc is 25 nanoseconds, and the maximum data throughput using the four-burst mode is approximately 6.4 Gigabits per second (Gbps). However, if consecutive memory accesses go to the same one of the four banks, the data throughput is reduced to approximately 2.5 Gbps, as a result of the Trc wait time.
As is apparent from the foregoing, a need exists for an improved DRAM-based memory architecture, for use in conjunction with a network processor or other processing device, which can provide the storage capacity and low power consumption advantages of DRAMs while also providing the advantage of SRAMs in terms of avoiding the problems associated with the above-described bank conflict penalty.